AD9550/PCBZ【PDF 6/8 页】BOARD EVALUATION FOR AD9550

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UG-203

LOOP FILTER

The internal portion of the loop filter has two configurations:

one is for low loop bandwidth applications (~170 Hz) and the

other is for medium (~20 kHz)/high (~75 kHz) bandwidth

applications. The low loop bandwidth condition applies when

the feedback divider value (N) is 2 14 (16,384) or greater. Other-

wise, the medium/high loop bandwidth configuration is in

effect. The feedback divider value depends on the configuration

of the A[3:0] and Y[5:0] pins per Table 4.

Evaluation Board User Guide

To achieve the best jitter performance in applications requiring

a loop bandwidth of less than 1 kHz, C1 and C2 must have an

insulation resistance of at least 500 ?F.

The evaluation board comes preconfigured with the external

loop filter components required for the low loop bandwidth

setting. However, it is good practice for any frequency select pin

combination to reference Table 5 for loop filter validation. For

more detail on the AD9550 loop filter, reference the AD9550

data sheet.

FROM

AD9550

PLL LOCKED INDICATOR

CHARGE

PUMP

375 ?

BUFFER

400k ?

3k ?

CONTROL

LOGIC

53pF

TO

VCO

The PLL provides a status indicator (LOCKED) that appears at

SMA Connector J2 and LED CR2. When the PLL acquires

phase lock, the LOCKED pin switches to a Logic 1 state. When

the PLL loses lock, however, the LOCKED pin returns to a

Logic 0 state.

SWITCHES CHANGE

STATE FOR N ≥ 16384

170pF

USING DIP SWITCHES

16

FILTER

17

LDO

1.

Determine the desired reference input frequency, output

frequencies, and output drivers by referencing Table 2,

R

Table 3, and Table 1 respectively and set the DIP switches

C1

C2

2.

appropriately.

Reference Table 5 to confirm the preprogrammed loop

The 20 kHz loop bandwidth case only applies when the A[3:0] pins = 1110

Figure 2. External Loop Filter

The bandwidth of the loop filter primarily depends on three

external components: R, C1, and C2 (labeled on the evaluation

board as R48, C15, and C3, respectively). There are two sets of

recommended values for these components corresponding to

the low and medium/high loop bandwidth configurations (see

Table 5. External Loop Filter Components

Loop

A[3:0] Pins R C1 C2 Bandwidth

0001 to 1100 and 1111 6.8 k? 47 nF 1 μF 0.17 kHz

1110 1 12 k? 51 pF 220 nF 20 kHz

1101 to 1110 12 k? 51 pF 220 nF 75 kHz

1

and the Y[5:0] pins = 111111.

3.

4.

5.

6.

bandwidth and that the components of the evaluation

board external loop filter match those required to the

current frequency select pin combination.

Set up the power and signal connections to the evaluation

board according to the Evaluation Board Hardware

section.

Toggle the RESETB DIP switch, to apply the pin settings

and calibrate the VCO.

Confirm that the PLL is locked by observing the lock

detect signal via LED CR2 or SMA Connector J2. If this

signal is low, confirm the reference input frequency and

external loop filter components. If these are correct, initiate

another VCO calibration by toggling the RESETB DIP

switch again.

Observe the output via the connected lab measurement

equipment.

Rev. 0 | Page 6 of 8

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